As semiconductor fabrication technology continues to progress, devices such as trench metal-oxide-semiconductor field effect transistors (TMOSFET) continue to get smaller and less expensive. The design and layout for such devices are constrained by technology specific minimum sizes, spacings, alignments and overlaps of the various structures of the semiconductor device and the fabrication means.
Referring to FIG. 1, a block diagram of a trench metal-oxide-semiconductor field effect transistor (TMOSFET) according to the conventional art is shown. As depicted in FIG. 1, the substrate of the TMOSFET includes a core area 105 and a termination area 110. A polysilicon layer is deposited on the substrate 115 and fills a plurality of trenches therein. A trench mask and a selective etching process is utilized to pattern the polysilicon layer after it is deposited on the substrate such that a plurality of gates 120 are formed in the trenches. A portion of the polysilicon layer in the termination area 110 is protected by the trench mask such that a first portion of a gate interconnect 125 is formed. A thick oxide layer 130 is then deposited in the termination area 110 and patterned such that a gate interconnect opening is formed. Another polysilicon layer is deposited and patterned to form a second portion of the gate interconnect 125. Another thick oxide layer 135 is deposited and patterned, such that a gate contact opening is formed. A gate contact 140 extends down through the gate contact opening, such that the gate contact 140 is electrically coupled the gates 120 by the gate interconnect 125.
Referring now to FIG. 2, a block diagram of another TMOSFET according to the conventional art is shown. As depicted in FIG. 2, the substrate of the TMOSFET includes a core area 205 and a termination area 210. A gate bus trench in the termination area 210 is formed having a greater width than the gate trenches in the core area. The width of the gate bus trench is greater than gate trenches in the core area 205 to enable ready alignment of the gate contact opening with the gate bus trench. A polysilicon layer is deposited on the substrate and fills the plurality of gate trenches and the gate bus trench. A trench mask and a selective etching process is utilized to pattern the polysilicon layer after it is deposited on the substrate, such that a plurality of gates 215 are formed in the gate trenches and a gate bus 220 is formed in the gate bus trench. A thick oxide layer 225 is then deposited and patterned such that a gate contact opening is aligned with the gate bus trench. A gate contact 230 extends down through the gate contact opening such that the gate contact 230 is electrically coupled to the gates 215 by the gate bus 220.
The structure of the TMOSFET as shown in FIG. 1 suffers in that the topology of the surface contains large height variations. The photolithography process utilized to pattern the various layers is adversely effected by the large height variations. The photolithography process has a restricted depth of focus that adversely impacts resolution limit (e.g., minimum feature size) which can be achieved utilizing photolithography because the topography height variations. Although the structure of the TMOSFET as shown in FIG. 2 has a substantially planar topography, the minimum feature size of the device is deleteriously affected by alignment requirements. Even a small misalignment in the exposure tool may result in increased leakage current or even an electrical short between the gate and source electrodes. In addition the TMOSFET structure as shown in FIG. 2 does not readily facilitate the integration of termination structures, such as a temperature sensor, an electro-static protection diode, a field capacitor and/or the like, as the entire polysilicon layer from which such structures may be formed is etched away.